module FSM(clk, rst, in, out);
	parameter S0 = 2'b00;
	parameter S1 = 2'b01;
	parameter S2 = 2'b10;
	parameter S3 = 2'b11;
	
	input	[1:0]	in;
	input			clk;
	input			rst;
	output	[3:0]	out;
	reg		[3:0]	out;
	reg		[1:0]	current_state;
	reg		[1:0]	next_state;
	
	//复位和状态转移操作,rst为0则复位，否则进入下一个状态
	always @(posedge clk or negedge rst) begin
		if(!rst)
			current_state <= S0;
		else
			current_state <= next_state;
	end
	
	//组合逻辑描述状态转移方式
	always @(in, current_state) begin
		case(current_state)
			S0: begin
				out = 5;
				if(in == 2'b00)
					next_state = S0;
				else
					next_state = S1;
			end
			S1: begin
				out = 8;
				if(in == 2'b00)
					next_state = S1;
				else
					next_state = S2;
			end
			S2: begin
				out = 12;
				if(in == 2'b11)
					next_state = S0;
				else
					next_state = S3;
			end
			S3: begin
				out = 14;
				if(in == 2'b11)
					next_state = S3;
				else
					next_state = S0;
			end
		endcase
	end

endmodule